SRAM memories in advanced technology nodes consume significant amount of leakage power. Powering down memories when not in use for long periods is one of the methods used to reduce overall power consumption in a system on a chip (SOC). However, memories that are shared by multiple masters need special handling for power down and wakeup. The problem is compounded in the case of federated memory controller architectures where the controller logic is split into master-specific and target specific blocks. In such a shared memory controller there is both per-CPU and per-bank logic.
In such architectures, different accesses may be in flight in different portions of the logic, when a request for power down is made from one or more masters. These accesses need to be completed before powerdown can take place. Similarly, when a wake-up occurs all components of the federated architecture must be informed so resume their normal operation which would have been suspended when the powerdown occurred.